1. Field of the Invention
The present invention relates to a communication data controller, and particularly to a communication data controller to carry out communication by writing transmission data on a FIFO (First-In First-Out) memory.
2. Description of the Related Art
Communication devices or the like have a communication data controller being equipped with a FIFO memory to control receiving and transmitting of data. The communication data controller, when receiving transmission data from a controlling device such as a CPU (Central Processing Unit) or the like, transmits the transmission data independently from the controlling device to a party with which communication is carried out. This enables decrease in a processing load on the controlling device.
Moreover, in the communication data controller, since transmission data is written on the FIFO memory, when an error or the like occurs during data transmission, by controlling an address of the transmission data stored in the FIFO memory, the transmission data can be retransmitted without rewriting of the transmission data (see, for example, Japanese Unexamined Patent Publication Nos. 2000-10758 and Hei 5-257847).
FIG. 6 shows an example of a circuit of a conventional communication data controller. As shown in FIG. 6, the communication data controller 101 is connected to a CPU 121 via a bus 122. Also, the communication data controller 101 is connected to a transmitting circuit 131 to transmit data and to a receiving circuit 132 used to receive data. A foldover wiring 133 is connected between the transmitting circuit 131 and the receiving circuit 132 so that transmission data output from the communication data controller 101 to the transmitting circuit 131 can be monitored. The transmitting circuit 131 and receiving circuit 132 are further connected to other communication device being a party with which communication is carried out.
The CPU 121, when transmitting transmission data to the communication device being the party with which communication is carried out, writes the transmission data on a buffer 102 in the communication data controller 101. The buffer 102 writes the written data on the FIFO memory 104. The write pointer 105 generates an address of the FIFO memory 104. The write pointer controller 106 controls the address generation to be performed by the write pointer 105. For example, the write pointer controller 106, when the transmission data stored in the buffer 102, exercises control so as to increment the address generated by the write pointer 105. Also, the write pointer controller 106, when the address generated by the write pointer 105 becomes a last one, exercises control so as to make the last address become a head address. The read pointer 107 generates an address used to read out transmission data from the FIFO memory 104. The read pointer controller 108 controls the address generation to be performed by the read pointer 107. For example, the read pointer controller 108, when transmission data is read out from the FIFO memory 104, controls so as to increment the address generated by the read pointer 107. Also, the read pointer controller 106, when the address generated by the read pointer 107 becomes a last one, exercises control so as to make the last address become a head address. Moreover, the write pointer controller 106 and the read pointer controller 108 control the address of the FIFO memory 104 so that the transmission data is written or read according to the FIFO method. The transmission data read from the FIFO memory 104 is transmitted to a communication device through the buffer 103 and the transmitting circuit 131. The reload pointer 109 stores an address of the transmission data to be retransmitted when transmission of data fails. The address of the reload pointer 109 is controlled by the CPU 121 (In FIG. 6, a line between the CPU 121 and the reload pointer 109 is omitted).
The CPU 121, when writing a block of transmission data on the FIFO memory 104, controls so as to store an address of the FIFO memory 104 on which a head of the block has been written in the reload pointer 109. Therefore, when a request for retransmission of transmission data is made, by setting an address of the reload pointer 109 to the read pointer 107, a block containing transmission data which has been requested to be retransmitted is retransmitted from the FIFO memory 104. Moreover, transmission data has a certain size and is, for example, one byte of data. The block is a collection of data and, for example, the block is delimited appropriately so that one block makes up one piece of data. How the block is delimited is judged by the CPU 121.
The receiving controller 110 judges whether or not retransmission of data is necessary. For example, the receiving controller 110 judges that the transmission of data is necessary when an error occurs in communications from a communication device being a party with which communication is carried out or when transmission data being monitored by the foldover wiring 133 is different from the transmission data or the like. The receiving controller 110, when judging that the retransmission of data is required, transmits a retransmission trigger signal RT to the read pointer controller 108.
The read pointer controller 108, when receiving the retransmission trigger signal RT from the receiving controller 110, controls the reload pointer 109 so as to set an address of the reload pointer 109 to the read pointer 107. As a result, a block of transmission data being stored in the FIFO memory 104 is read out, beginning with its head of the block, and is retransmitted to a communication device.
The receiving circuit 132 receives receiving data from the communication device being a party with which communication is carried out. The receiving circuit 132 writes received data on the buffer 114. The buffer 114 writes the written data on the FIFO memory 111.
The write pointer 115 generates an address used to write the received data on the FIFO memory 111. The read pointer 113 generates an address used to read out the received data written on the FIFO memory 111. The received data read out from the FIFO memory 111 is output to the CPU 121 through the buffer 112 and the bus 122. Moreover, in FIG. 6, a pointer controller to control address generation to be performed by the read pointer 113 and write pointer 115 is omitted. The pointer controller controls the address of the FIFO memory 111 so that the transmission data is written or read according to the FIFO method.
However, when a block of transmission data to be transmitted to a party with which communication is carried out exceeds a capacity of the FIFO memory, transmission data exceeding the capacity of the FIFO memory must be overwritten on an area in which transmission of data has already been completed. Therefore, there is a problem that, if necessity of the retransmission of a block arises, the transmission data has been partially lost in the FIFO memory, thus making it impossible to correctly retransmit the data stored in the FIFO memory.
FIG. 7 shows a diagram explaining a state of a FIFO memory occurring when a block of transmission data exceeds a capacity of the FIFO memory. In FIG. 7, a block 141 of transmission data to be transmitted to a communication device of a party with which communication is carried out is shown. The double-headed arrow A101 shows a capacity of the FIFO memory of the transmission data controller 101. As shown in FIG. 7, since the capacity of the block 141 exceeds the capacity of the FIFO memory, a portion of the block 141 that exceeds the capacity of the FIFO memory, that is, a portion shown by the double-headed arrow is overwritten on a FIFO memory area in which transmission of data has been already completed. Therefore, if necessity of retransmission of the block 141 arises, the transmission data has been partially lost and, as a result, it is impossible to retransmit correct transmission data from the FIFO memory.
Moreover, when the transmission of a block of transmission block has not yet been completed, if a subsequent block is written on the FIFO memory, an address of the subsequent block is stored in the reload pointer. Therefore, a problem arises that, if necessity of retransmission of a block existing before a newest block arises, an address of the block to be retransmitted has been lost and the retransmission is made impossible.
FIG. 8 shows a diagram explaining a state of a read pointer occurring when a block of transmission data is written on a plurality of FIFO memories. In FIG. 8, a plurality of blocks 151 to 153 written on the FIFO memory is shown. Now let it be assumed that, during transmission of the block 151, the blocks 152 and 153 are written, without being overwritten, on the FIFO memory. In this case, an address of the FIFO memory in which a head of the block 153 has been stored is stored in the reload pointer 109. Therefore, during the transmission of the block 151 or the block 152, if a request for the retransmission of transmission data is made, since the address of the reload pointer 109 has been changed, which makes it impossible to retransmit the data.